The AI development trend is focused on improving efficiency in data movement and access, such as data bandwidth and transmission speed. In particular, with the recent dominant market share increase of DDR5 and the expected 212% growth rate in a new type of DRAM called CXL memory, the utilization of chip solutions that satisfy performance in data-intensive applications is becoming prominent.

AMD unveiled the 2nd generation Versal Premium series, which supports CXL 3.1, PCIe Gen 6, and LPDDR5X in the form of hard IP for the first time in the FPGA industry, through a media pre-briefing on the 12th.

These next-generation interface and memory technologies contribute to efficient handling of data movement and access between processors and accelerators.
CXL 3.1 and LPDDR5X can utilize more memory resources faster, meeting the real-time processing and storage requirements of data-intensive applications such as data centers, communications, test and measurement, and aerospace and defense.

“AMD is targeting applications and markets that demand data-intensive performance,” said Mike Larder, senior manager of product marketing at AMD. “The space, aerospace and defense market is powered by small form factors; the communications market is powered by AI-based 6G RAN acceleration; the data center market is powered by AI-based custom networking and enterprise SSDs; and the test and measurement market is powered by protocol analyzers and camera sensors.”

The 2nd generation Versal Premium devices support high-bandwidth host CPU-to-accelerator connections via the latest PCIe Gen 6 and CXL 3.1. Additionally, system developers can leverage the latest AMD FPGA-based devices connected to high-performance CPUs via CXL/PCIe, leveraging the 2nd generation Versal Premium series and AMD EPYC CPUs simultaneously.

AMD cited memory performance as a strong advantage that the 2nd generation Versal Premium has over competing products in its class. Memory bandwidth has been improved with LPDDR5X, the fastest memory standard currently available with a maximum speed of 8,533 Mb/s, improving data transmission and real-time response speed.

Additionally, by connecting with the CXL memory expansion module, it is possible to utilize up to 2.7 times higher total bandwidth than when using only LPDDR5X memory. This allows the 2nd generation Versal Premium series to optimize memory utilization and increase memory bandwidth and capacity by supporting memory pooling that can be expanded and dynamically allocated to multiple accelerators.

The 2nd generation Versal Premium Series adaptive SoCs improve memory utilization of multi-headed single logic devices (MH-SLDs) by dynamically allocating memory pools across multiple devices. This enables operation without the use of fabrics or switches, and supports up to two CXL hosts.

The 2nd generation Versal Premium series with enhanced security features is an FPGA that supports PCIe Integrity and Data Encryption (PCIe IDE) integrated in the form of hard IP. Inline encryption built into the hardware-structured DDR memory controller protects data at rest, and the 400G high-speed encryption engine allows the device to protect user data at up to twice the speed.

AMD's 2nd generation Versal Premium series development tools are expected to be released in the second quarter of 2025, with silicon samples expected in early 2026. Production products are expected to ship in the second half of 2026.