Keysight Technologies, Inc. has upgraded its high-speed digital chiplet design solutions for AI and data center applications, helping chiplet designers build more precise systems and achieve optimal performance.

Keysight recently launched 'Chiplet PHY Designer 2025'.

This upgrade adds simulation capabilities for the Universal Chiplet Interconnect Express™ (UCIe™) 2.0 standard, as well as new support for the Open Compute Project (OPC) and Bunch of Wires (BoW) standards.

Chiplet PHY Designer 2025 is an advanced system-level chiplet design and die-to-die (D2D) design solution that enables pre-silicon verification, helping designers move more efficiently through the tapeout process.

As AI and data center chips become increasingly complex, reliable communication between chiplets is emerging as a critical factor in determining system performance.

To address this, the industry is adopting open standards such as UCIe and BoW, which play a key role in defining the interconnection method between chiplets in 2.5D/3D packaging and advanced packaging technologies. />
Chiplet PHY Designer 2025 provides design verification capabilities compliant with UCIe 2.0 and BoW standards, enabling seamless integration of chiplets into the modern packaging ecosystem.

It also supports automatic simulation and compliance test setup, such as Voltage Transfer Function (VTF), to help increase accuracy in the early stages of design.

Chiplet PHY Designer 2025 helps reduce the risk of silicon re-spins through signal integrity and bit error rate (BER) and crosstalk analysis, and also supports analysis of advanced clocking techniques such as quarter-rate data rate (QDR), enabling more precise clocking system implementation.

“This update is a tool that helps chiplet designers verify their specifications quickly and accurately before tapeout,” said Hee-Soo Lee, director of Keysight EDA’s High-Speed Digital division. “This latest version reflects new standards and enables designers to perform verification faster and more accurately.”