“The next-generation intelligent semiconductor project, jointly conducted by the Ministry of Science and ICT and the Ministry of Trade, Industry and Energy, aims to overcome the limitations of existing semiconductors and develop new devices with ultra-low power and high performance. Researchers have been focusing on discovering key element technologies for the past five years, and starting this year, they are promoting the advancement of key candidate technologies.”

Lee Seok-hee, team leader of the Next Generation Intelligent Semiconductor Business Unit's Component Team, presented the '2025 Next Generation Intelligent Semiconductor Technology Development Project Component Sector Implementation Status' at the '2025 Neuromorphic Semiconductor Workshop' held at E-Tower on the 19th.

Team Leader Lee Seok-hee said that next-generation semiconductor research is being conducted in three directions: development of new device source technology, direct verification technology, and development of new concept basic technology. He added that in particular, research is being focused on six major areas: improving information density, smart wiring, microcurrent control, three-dimensional integration, and brain simulation.

The government spared no support for the implementation of vertical integration and 3D integration platforms through the development of direct verification technologies for the first 3 to 4 years, and conducted open competitions for the development of new concept material technologies to enable creative research. It was reported that it was being promoted.

The brain simulation field is currently investing a total of 48.3 billion won in 17 projects, and is spurring the securing of next-generation memory source technologies and the development of ultra-low-power devices. The researchers said that rather than completely replacing existing CMOS, the new devices are moving in the direction of implementing new architectures through fusion.

In particular, domestic researchers are focusing on developing AI processors based on new components. The main goal is to build an architecture that can be replaced with new components and secure next-generation memory technology. Phase 1 research has been conducted until 2022, and Phase 2 research is currently underway.

Recently, NFC-based service platform construction and advancement of component modeling technology through RSA have been carried out, and the ultimate goal is to implement a 1mW-class analog processor.

The researchers plan to improve performance by optimizing new devices and advancing modeling technology.

Domestic researchers are aiming to secure world-class performance through the development of various new devices.

We are researching various technologies such as ferroelectrics, resistive elements, and seat bodies, and are pursuing fusion with existing CMOS-based artificial intelligence processors.

Additionally, researchers have recently developed a neuromorphic chip to demonstrate autonomous driving simulations using damage compensation.

Research institutes and universities are implementing 4K-class arrays and developing high-density new device technologies.

Team Leader Lee Seok-hee said, “The research team aims to complete the next-generation semiconductor technology with a computational performance of 1 teraflop by implementing a prototype by 2029,” and “To this end, we will secure source technology, design cores, and build platforms.”

He also said, “By building a public infrastructure based on NNFC, we are creating an environment where researchers can directly design new devices at the wafer level, and we are expanding the possibility of performance verification and utilization through the DDI tab.”