■ The design process for multiphase parallel structures involves significant complexity

Powering the core rails of high-performance FPGAs (Field Programmable Gate Arrays) and ASICs (Application-Specific Integrated Circuits) requires both high current and precise transient response control.

The rapid advancement of FPGAs, ASICs, and related systems in recent years has increased complexity, and significant updates to power supply specifications have become necessary to address this.

A suitable design for this requires a delicate balance between efficiency, dynamic response, and the size and power loss of the MOSFET.

The most commonly used method to meet these demanding power supply requirements is to arrange multiple power supplies in parallel.

Parallel configuration allows for the supply of necessary power more easily and efficiently by distributing current evenly between each power supply (often called a phase).

Furthermore, to further improve performance, a phase difference can be set between each power supply branch.

This effectively reduces overall current and voltage ripple, thereby improving power quality.

However, the process of designing such a multiphase parallel structure involves considerable complexity.

The phases must be accurately distributed, and the currents between all phases must be perfectly balanced. This is because it needs to be controlled.

Securing accurate phase distribution and current balance is key to building high-performance power systems, but it remains a challenge that still needs to be solved.

To meet the low voltage and high current conditions required by the core rails of FPGAs and ASICs and to solve the problem of precise transient response control, modern power systems are being designed to operate at higher switching frequencies by applying multiphase power solutions.

Integrated power modules such as the MPM3698 and MPM3699 have emerged to simplify complex multiphase power systems and design processes.

These modules internally implement advanced multiphase control methods, including automatic interleaving and phase shedding.

This allows designers to avoid complex current balancing and phase synchronization issues, thereby ensuring design ease.

This article will explain the design process of multiphase converters in detail and cover the key factors to consider when designing multiphase power supplies.

■ FPGA and ASIC Design Requirements

When developing power supplies for FPGAs and ASICs, the primary factor to consider is the voltage requirements for various power rails.

Looking at the voltage rail standards of typical FPGAs and ASICs, the input voltage (VIN) is usually 12V, the output current (ITDC) is about 180A, and the output voltage (VOUT) is about 1.2V.

[Table 1] below shows the voltage requirements of typical FPGAs. This example is based on the Spartan-7 FPGA.


Core/Aux and input/output voltage information for various FPGA models currently on the market is presented in [Table 2].


As can be seen from the two tables presented earlier ([Table 1] and [Table 2]), the voltage regulations for FPGAs are very strict.

Since voltage tolerances in most modern FPGA systems are within ±3%, the designed power supply must provide extremely precise voltage characteristics.

The most effective way to meet these stringent voltage regulations is to apply a multiphase power supply system.

■ Principles and Benefits of Multiphase Power Supply Systems

In multiphase power supply designs, the system's fundamental frequency is effectively increased by the number of phases used.

This results in an increased ripple frequency at the output stage, ultimately providing higher current capacity with a smaller board area and less output capacitance.

Buck converters used in FPGA and ASIC applications must have fast transient response capabilities.

In other words, it must be possible to transfer energy very quickly from the input to the output.

When using a parallel converter to supply power to a load, each branch operates with an equal phase difference.

This reduces steady-state voltage ripple and lowers input and output RMS currents.

As a result, the entire solution can operate stably with only a smaller number of input and output capacitors.

By utilizing this multiphase method, current ripple can be effectively reduced, and by enabling the use of smaller inductors, the effect of reducing even transient voltage spikes can be achieved.

Due to the frequency multiplication effect, the amplitude of the output ripple is divided by the number of branches (phases) used (N), and the ripple frequency increases by N.

For example, looking at the case of a 4-phase application, the total inductor current ripple (IOUT = IO1 + IO2 + IO3 + IO4) becomes four times smaller than the ripple of individual phases, and the ripple frequency increases four times compared to the individual phase frequency (see Figure 1).