Provides 9% improved performance at the same power compared to Intel 18A, and reduces power consumption by 18% at the same performance.

Intel Foundry announced its process roadmap and long-term research results at the 2026 VLSI Symposium. Intel 18A-P, the first performance-accelerated version of the Intel 18A product family, has entered the Risk Production phase, and mid-to-long-term research and development achievements, including next-generation transistors and wiring technology, were also unveiled.

Intel Foundry announced on the 17th that its Intel 18A-P process has entered the test production phase, stating that this is in accordance with the roadmap schedule shared with customers and partners last year.

"Technological innovation is a continuous journey and there are challenges ahead, but I am pleased to share the progress we are making in Intel's 18A-P process and mid-to-long-term research and development," said Naga Chandrasekaran, Executive Vice President of Intel Foundry.

Intel Foundry explained that the Intel 18A-P provides 9% improved performance at the same power compared to the Intel 18A, or reduces power consumption by 18% at the same performance.

Key technological advancements include a dual-contact transistor option called 'Power Boost' that increases driving current, a 20-40% improvement in thermal resistance, a 10-30% reduction in via resistance, and improved PMOS mobility.

In addition, they stated that they have expanded the range of speed and power balance adjustments by adding a fifth logic Vt pair between ULVT and LVT.

Intel 18A-P is reported to be fully compatible with Intel 18A's design rules, allowing existing IP and design flows to be reused as is.

It supports two cell heights (180nm and 160nm) and 50nm CPP.

Intel Foundry also released quantification results for Gate-All-Around (GAA) transistors and Back-Side Power Delivery (BSPD) technology.

Fellow Eric Karl reduced routing area by 11% and dynamic voltage drop tenfold with this technology. They stated that they reduced it.

Intel Foundry announced that future innovation areas include a monolithic CFET inverter that vertically stacks NMOS and PMOS at a 45nm gate pitch, a technology that integrates GaN power devices and silicon logic onto a 300mm wafer, and subtractive ruthenium wiring that reduces parasitic capacitance by up to 35% compared to copper.